1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a circuit for driving a nonvolatile ferroelectric memory.
2. Background of the Related Art
Generally, a nonvolatile ferroelectric memory, i.e., a ferroelectric random access memory (FRAM) has a data processing speed equal to a dynamic random access memory (DRAM) and retains data even in power off. For this reason, the nonvolatile ferroelectric memory has received much attention as a next generation memory device.
The FRAM and DRAM are memory devices with similar structures, but the FRAM includes a ferroelectric capacitor having a high residual polarization characteristic. The residual polarization characteristic permits data to be maintained even if an electric field is removed.
FIG. 1 shows hysteresis loop of a general ferroelectric. As shown in FIG. 1, even if polarization induced by the electric field has the electric field removed, data is maintained at a certain amount (i.e., d and a states) without being erased due to the presence of residual polarization (or spontaneous polarization). A nonvolatile ferroelectric memory cell is used as a memory device by corresponding the d and a states to 1 and 0, respectively.
A related art nonvolatile ferroelectric memory device will now be described. FIG. 2 shows unit cell of a related art nonvolatile ferroelectric memory.
As shown in FIG. 2, the related art nonvolatile ferroelectric memory includes a bitline B/L formed in one direction, a wordline W/L formed to cross the bitline, a plate line P/L spaced apart from the wordline in the same direction as the wordline, a transistor T1 with a gate connected with the wordline and a source connected with the bitline, and a ferroelectric capacitor FC1. A first terminal of the ferroelectric capacitor FC1 is connected with a drain of the transistor T1 and second terminal is connected with the plate line P/L.
The data input/output operation of the related art nonvolatile ferroelectric memory device will now be described. FIG. 3a is a timing chart illustrating the operation of the write mode of the related art nonvolatile ferroelectric memory device, and FIG. 3b is a timing chart illustrating the operation of read mode thereof.
During the write mode, an externally applied chip enable signal CSBpad is activated from high state to low state. At the same time, if a write enable signal WEBpad is applied from high state to low state, the write mode starts. Subsequently, if address decoding in the write mode starts, a pulse applied to a corresponding wordline is transited from low state to high state to select a cell.
A high signal in a certain period and a low signal in a certain period are sequentially applied to a corresponding plate line in a period where the wordline is maintained at high state. To write a logic value "1" or "0" in the selected cell, a high signal or low signal synchronized with the write enable signal WEBpad is applied to a corresponding bitline.
In other words, a high signal is applied to the bitline, and if the low signal is applied to the plate line in a period where the signal applied to the wordline is high, a logic value "1" is written in the ferroelectric capacitor. A low signal is applied to the bitline, and if the signal applied to the plate line is high, a logic value "0" is written in the ferroelectric capacitor.
The reading operation of data stored in a cell by the above operation of the write mode will now be described. If an externally applied chip enable signal CSBpad is activated from high state to low state, all of bitlines become equipotential to low voltage by an equalizer signal EQ before a corresponding wordline is selected.
Then, the respective bitline becomes inactive and an address is decoded. The low signal is transited to the high signal in the corresponding wordline according to the decoded address so that a corresponding cell is selected.
The high signal is applied to the plate line of the selected cell to destroy data corresponding to the logic value "1" stored in the ferroelectric memory. If the logic value "0" is stored in the ferroelectric memory, the corresponding data is not destroyed.
The destroyed data and the data that is not destroyed are output as different values by the ferroelectric hysteresis loop, so that a sensing amplifier senses the logic value "1" or "0". In other words, if the data is destroyed, the "d" state is transited to an "f" state as shown in hysteresis loop of FIG. 1. If the data is not destroyed, "a" state is transited to the "f" state. Thus, if the sensing amplifier is enabled after a set time has elapsed, the logic value "1" is output in case that the data is destroyed while the logic value "0" is output in case that the data is not destroyed.
As described above, after the sensing amplifier outputs data, to recover the data to the original data, the plate line becomes inactive from high state to low state at the state that the high signal is applied to the corresponding wordline.
FIG. 4 illustrates a block diagram of a related art nonvolatile ferroelectric memory. As shown in FIG. 4, the related art nonvolatile ferroelectric memory is provided with a main wordline driver 41, a first cell array 43 on one side of the main wordline driver 41, a first local wordline driver 45 on one side of the first cell array 43, a second local wordline driver 47 on one side of the first local wordline driver 45 and a second cell array 49 on one side of the second local wordline driver 47. A first local X decoder 51 is formed over the first local wordline driver 45, and a second local X decoder 53 formed over the second local wordline driver 47. The first local wordline driver 45 is adapted to receive a signal from the main wordline driver 41 and a signal from the first local X decoder 51 and selects a wordline for the first cell array unit 43. The second local wordline driver 47 is adapted to receive a signal from the main wordline driver 41 and a signal from the second local X decoder 53 and selects a wordline for the second cell array 49. The related art nonvolatile ferroelectric memory provides a signal from the main wordline driver 41 both to the first and second local wordline drivers 45 and 47. Therefore, one of the first and second cell arrays 43 and 49 is selected depending on signals from the first local X decoder 51 and the second local X decoder 53. That is, either the first cell array 43 or the second cell array 49 is selected, and a wordline of the selected cell array is driven depending on signals from the first and second local X decoders 51 and 53.
FIG. 5 is a diagram that illustrates selection of one of the cell arrays depending on signals from the first and second local X decoders 51, 53 of FIG. 4. As shown in FIG. 5, the main wordline connected to the main wordline driver 41 is formed across the first and second local wordline drivers 45 and 47 and the first and second cell arrays 43 and 49. The first local wordline driver 45 is a NAND logic gate 55 for subjecting a signal from the main wordline driver 41 received through the main wordline and a signal from the first local X decoder 51 to an logical operation. An output of the logic gate 55, the NAND gate, is dependent on signals from the first and second local X decoders 51 and 53 regardless of the signal provided from the main wordline driver 41. For example, if it is assumed that a high signal is provided from the main wordline driver 41, the first cell array 43 is selected if a signal from the first local X decoder 51 is low and a signal from the second local X decoder 53 is high. Opposite to this, if a signal from the first local X decoder 51 is high and a signal from the second local X decoder 53 is low, the second cell array 49 is selected. Thus, selection of either of the first and second cell arrays is dependent on the signals from the first and second local X decoders 51 and 53. As described above, the circuits for driving a nonvolatile ferroelectric memory shown in FIGS. 4 and 5 are limited portions. Thus, there are a plurality of first and second local wordline drivers 45 and 47, the first and second cell arrays 43 and 49, and first and second local X decoders 51 and 53.
As described above, the related art circuit for driving a nonvolatile ferroelectric memory has various disadvantages. The two local X decoders required for selection of either one of the left or right cell array occupy a large area. Such an area increase, even if the area should become smaller according to the trend of high density device packing, causes delays that drop an access speed and deteriorate a driving performance. Further, an increase in chip size is not favorable for device packing or cost.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.